The present invention relates generally to a semiconductor manufacturing process, and more particularly to a method for formation of spacers in a semiconductor manufacturing process.
The main technology for ultra large-scale integrated (ULSI) circuits is Complementary Metal-Oxide-Semiconductor (CMOS) technology. High-performance CMOS technologies commonly employ various processes to form offset spacers, nitride spacers, and Self-ALIgned SiliCIDE (salicide) formation. Offset spacers-0 serve to place e.g., shallow source/drain (S/D) extensions and/or halo implants some distance, e.g., 5 to 20 nm, from a gate edge. Varying the width of the offset spacers-0 has been used to adjust the channel lengths of the P-channel MOS (PMOS) and N-channel MOS (NMOS), as well as to reduce the overlap capacitance, known as the Miller capacitance, between the gate electrode and the source/drain (S/D) region. Spacers in general serve also to place, e.g., deep S/D implants from the gate. In addition, spacer-0s have been used for several other types of implant processes, e.g., xenon pre-amorphization implants. Offset spacers typically consist of silicon oxide or silicon nitride.
While increasing the width of spacer-0 decreases the overlap between S/D extensions and the gate, thus reducing the Miller capacitance and improving device performance, if spacer-0 is too wide, a condition referred to as xe2x80x9cunder-lapxe2x80x9d occurs. With under-lap, the S/D extensions no longer reach the gate and device performance degrades. Hence, it is important to control the width of spacer-0 during device manufacture.
CMOS-technologies regularly employ both NMOS and PMOS transistors within the same device, as seen in FIG. 1. FIG. 1 illustrates a cross-sectional view of a MOSFET device 100 manufactured with both a PMOS transistor 110 and NMOS transistor 115 according to the prior art. PMOS and NMOS transistors 110 and 115 utilize different dopant materials for S/D implantation. For example, arsenic (As) may be the implant species for the N-type implanted S/D extension areas 117 adjacent NMOS gate 118 and NMOS spacer-0 119, while another species such as boron (B) may be used for the P-type implanted S/D extension areas 121 adjacent PMOS spacer-0 123 and PMOS gate 125. NMOS and PMOS transistors 115 and 110 are separated by an isolation area 127, and are constructed on substrate 130. Details of the S/D areas 117 and 121 are not shown in FIG. 1.
During the thermal annealing required for the S/D extension areas 117 and 121 for dopant activation, the smaller boron atoms in extension areas 117 diffuse much more than those of the larger arsenic atoms in extension areas 121. As a result, the PMOS S/D extension areas 121 will have a larger overlap with PMOS gate 125 than will be the case with S/D extensions 117 and NMOS gate 118. When the width Z of spacer-0s 119 and 123 are the same, it is not possible to prevent this larger overlap in S/D extension 121 or underlap in S/D extension 117. To overcome this problem, process engineers have devised processes to adjust the width Z of spacer-0 123 independently of that of spacer-0 119. Creating different spacer-0 widths, or xe2x80x9cdifferentialxe2x80x9d spacer widths for the NMOS spacer-0 119 and the PMOS spacer-0 123, as seen in FIG. 2, solves the unequal diffusion problem.
FIG. 2 illustrates a cross-sectional view of a MOSFET device 200 created with differential spacers according to the prior art. As seen in FIG. 2, the width W of spacer-0 223 is wider than the width X of the NMOS spacer-0 219. The process sequence outline to form differential width spacers such as spacer-0 223 as shown in FIG. 2 typically proceeds as follows:
1. Deposit 100 Angstroms of silicon oxide overlying NMOS gate218, PMOS gate 225, substrate 230 and isolation area 227
2. Anisotropically etch the 100 Angstrom oxide, stopping on the silicon 217, 221, which leaves a 100 Angstrom thick spacer-0 on both NMOS and PMOS transistor gates (218 and 225)
3. Mask off PMOS transistor 210 with a photo resist mask
4. Implant S/D extensions 217 for NMOS transistor 215 using the 100 Angstrom spacer-0
5. Remove the photo resist protecting the PMOS transistor 210 regions
6. Deposit 50 Angstroms of silicon oxide overlying NMOS gate218, PMOS gate 225, substrate 230 and isolation area 227
7. Anisotropically etch the 50 Angstroms of silicon oxide, stopping on the silicon, which leaves spacer-0 223 with 150 Angstroms total width W
8. Mask off NMOS transistor 215 with a photo resist mask
9. Implant S/D extensions 221 for PMOS transistor 210 using the 150 Angstrom spacer-0 width (W)
10. Remove the photo resist protecting the NMOS transistor 215
There are various assumptions made in the process sequence of 1-10 above, e.g., the width values given are arbitrary values; no lateral etching occurs during the anisotropic etch; halo implants are not mentioned; and the NMOS transistor 215 may be made wider than the PMOS transistor 210 using the same process sequence. Should lateral etching occur, the process engineer generally compensates by increasing the deposition thickness of the silicon oxide accordingly. Halo implants are usually done together with the S/D extension implants, but may also be done at an earlier or later stage in the process sequence.
Although the process sequence outlined above addresses the diffusion problem, there are various drawbacks associated with the approach as well. For example, the process sequence requires at least two separate plasma etch steps. Plasma etch steps are expensive processes. In addition, oxide-spacer-0 etch processes result in some inherent silicon loss (silicon recess) in the S/D extension regions. Ideally, no recess should exist between the edges of the gates/spacer-0 and the active silicon, as device performance is adversely affected. In FIGS. 1 and 2, no silicon recess is illustrated. Unfortunately, in practice the etch process for an oxide spacer-0 typically seems to produce at least a 2.5 nm (25 Angstrom) recess per etch, with resultant device performance degradation. To minimize this silicon recess, the spacer-0 etch process should not etch even 1 or 2 nm into the active silicon. The second etch process (No. 7, above) step contributes further to silicon recess because the thin (50 Angstrom) oxide layer is difficult to control and endpoint. Using an etch endpoint is desirable in order to compensate for some variations, e.g., layer thickness variations, process chamber variations, and the like, and to reduce the amount of over-etch applied.
Therefore, a method for forming differential spacers during the CMOS production flow which overcomes the limitations of current processes would be useful.